(a) Field of the invention
The present invention concerns a static induction transistor having hetero-junction and semiconductor integrated circuit containing such transistor.
(b) Description of the prior art
A static induction transistor (hereinafter referred to as "SIT") is a new semiconductor device recently developed by J. Nishizawa, one of the inventors of the present invention, and has such excellent characteristics that it deserves being called a third type of transistor comparable to the bipolar transistor, (usually referred to simply as "transistor"), or to the unipolar field effect transistor (referred to as "FET"). The electric characteristics and the operating mechanism of the SIT was reported first in IEEE Trans. on Electronic Devices, vol. ED-22, pp 185-197, 1975. Thereafter, there have been conceived and proposed various applications of the SIT, utilizing the superior features thereof. The principle of operation of the SIT will now be briefly explained for clarity's sake.
An example of the structure of a known junction SIT is shown in FIG. 1. In the Figure, reference numeral 1 represents an n.sup.+ type source region having a high impurity concentration of the order of 10.sup.18 -10.sup.21 atoms/cm.sup.3. A source electrode 1a which is in ohmic contact with the n.sup.+ type source region 1. An n.sup.- type channel region 2 having a low impurity concentration of about 10.sup.12 -10.sup.15 atoms/cm.sup.3 plays an important role in operation of the SIT. It should be understood, however, that this n.sup.- type channel region is such that its conductivity type need not be n.sup.- type, but it may be a p.sup.- type region having an impurity concentration of about 10.sup.13 -10.sup.16 atoms/cm.sup.3. A p.sup.+ type gate region 4 has an impurity concentration of about 10.sup.18 -10.sup.20 atoms/cm.sup.3. A gate electrode 4a which is in ohmic contact with said p.sup. + type gate region 4. An n.sup.+ type drain region 3, cooperates with a drain electrode 3a which is in ohmic contact with said n.sup.+ type drain region 3. An insulating film 5 is formed with a material such as an oxide film. Across the source and the gate electrodes is formed a pn junction, so that when a reverse bias is applied thereacross, a depletion layer is formed in the channel region 2. Application of more intensive reverse bias will result in the growth of a broader depletion layer, and the condition in which the entire channel region is depleted can occur. It will be understood that if the width of the channel region is short and if the impurity concentration of the channel region is low, the channel region is easily depleted by the application of a low reverse bias. Depending on the design, the channel region will become depleted by the built-in potential alone (the externally applied voltage is nil), and thus the phenomenon that the channel region becomes a space charge region readily takes place.
If the channel region has become depleted as stated above, and an appropriated voltage is applied to the drain, the energy band structure at the center of the channel (indicated by line X-Y in FIG. 1) will become as shown in FIG. 2. The numeral 6 indicates the bottom of the conduction band CB, and the numeral 7 represents the top of the valence band VB. The flat region at the left-hand side indicates the potential at the n.sup.+ type source region 1, while the flat region at the right-hand side represents the potential at the n.sup.+ type drain region 3. There appears a potential barrier in front of the source region as shown in FIG. 2. In such condition, the electrons (which are the majority carriers in the n.sup.+ type source region 1) are unable to flow into the drain region side; electron flow is obstructed by the potential barrier developed in the channel region 2. Therefore, either by reducing the reverse voltage applied to the gate region or by applying a drain voltage, the potential barrier can be lowered due to electrostatic induction, to cause the electrons in the source region to flow to the drain. Thus, the mechanism of operation of the SIT resembles the operating principle of a triode vacuum tube, and the I-V characteristic of the SIT also resembles that of the triode vacuum tube.
As briefly explained above, a SIT is a transistor designed to control the amount of the majority carriers flowing from the source region to the drain region by varying electrostatically the potential distribution within the depletion layer developed in the channel region, i.e. the space charge region. Particularly the height of the potential barrier (portion higher than the bottom of the conduction band of the source region), by utilizing the voltage applied to the gate region and also by the voltage applied to the drain region. Voltage variation across the gate and source regions intensively contributes to the operation of this SIT. However, the current flowing across the gate and source regions is irrelevant and altogether unnecessary for the operation of the SIT. In other words, an SIT is a transistor having a current amplification factor which can be considered essentially infinite. In an SIT which is designed to have a narrow or small channel width and/or a low channel region impurity concentration, so that the depletion layer extends throughout the entire channel region without an applied reverse voltage to the gate-source pn junction, i.e. depleted by the built-in potential, the SIT will provide a so-called "normally-off" characteristic, whereby no drain current will flow unless a substantially high voltage is applied to the drain region. On the other hand, in an SIT of the type that no potential barrier is developed in the absence of a gate voltage, characteristic will be manifested, whereby called "normally-on" type drain current will begin to flow readily by the application of a drain voltage, because there is no potential barrier present. Normally-off type SITs are typically utilized in high-speed switching device, a memory device, and semiconductor integrated circuit, applications. In order to provide a normally-off semiconductor device, it is necessary to determine the impurity concentration of the channel region, taking into account the gate-to-gate distance, as well as the length of the channel to insure that the channel region is completely depleted in response to the built-in potential at the pn junction across the channel region and the p.sup.+ type gate region. Moreover, the channel length must be made longer than a certain value, for example, the gate-to-gate distance, to realize an excellent normally-off characteristic.
An application of forward gate bias voltage on the normally-off SIT tends to enable the drain current to flow. Forward gate bias operation of the normally-off SIT is called "bipolar mode SIT" (BSIT). BSIT has been demonstrated experimentally to be characterized by high current density in the "on" state irrespective of the relatively low impurity concentration in the channel, high-transconductance, low on-voltage, low impedance characteristic and so forth. The features of BSIT are very favorable to integrated circuit applications, because of its low power dissipation, high driving capability, high speed switching and so on.
Where a normally-off type SIT is used to perform, for example, a switching operation, i.e. it is intended to change the drain current from the "off" state to the "on " state, it is more desirable to lower the potential barrier to a certain lower level or to zero, and to change the "off" state to the "on" state by applying a forward bias across the pn junction between the gate and source region under a given constant drain voltage applied, rather than lowering the potential barrier and causing a drain current to flow by the application of a more intensive drain voltage.
It should be noted, however, that in such arrangement of device as described above, the gate-source pn junction, can give rise to various problems and hence to accompanying undesirable phenomenons. That is, if a pn junction is formed across the gate and source regions, an application of a forward bias will result in mutual injections of minority carriers into the gate and source regions, causing a gate current to flow. Here, it will be noted that in view of the impurity concentrations of the p.sup.+ type gate region and the n.sup.- type channel region, most of the minority carrier injection takes place from the gate region into the source region. If this minority carrier injection takes place, and causes a gate current flow, a marked lowering of the current gain (which otherwise can take a value nearly infinite) will result. Not only does a lowering of the current amplification factor result from such leakage current, but also, due to the storage effect due to the prolonged relaxation time or prolonged lifetime of the injected minority carriers, the frequency characteristic of the operation of an SIT is degraded. Also, if a known junction SIT which is operated at forward gate bias is incorporated in a semiconductor integrated circuit, the minority carrier injection will become a limiting factor on the number of fan-outs to be taken and the propagation delay time which are the features of the integrated circuit.
Basic transport phenomenon in BSIT will be briefly described hereinafter by using a rectangular channel device, where the gate-to-gate distance is denoted by D, and the source-to-drain distance, i.e., the channel length in this device, is defind by L. The transport phenomenon has been introduced by using the numerical simulation based on Poisson's equation and carrier continuity equations.
Source-to-drain potential distributions along the channel center are illustrated for various gate bias voltages V.sub.G in FIG. 3, where the drain voltage is set at 1.0 V. Typical device parameters are as follows. The values of D and L are 0.8 .mu.m, and 1.2 .mu.m, respectively. The impurity concentration is 1.times.10.sup.14 cm.sup.-3 in the channel, 1.times.10.sup.19 cm.sup.-3 in the source region, 1.times.10.sup.18 cm.sup.-3 in the gate region and 1.times.10.sup.17 cm.sup.-3 in the drain region. FIG. 4 shows the spatial distribution of electron and hole concentrations from source to drain along the channel center for the same operational condition as in FIG. 3, where the solid line represents the electron concentration, and the dashed line represents the hole concentrations. Spatial distribution of the electron and the hole concentration in the crosswise direction of the channel passing through the potential barrier height is shown for the same operational condition in FIG. 5, where the solid line represents the electron concentration and the dashed line represents the hole concentration. The increase of the gate bias voltage decreases the potential barrier height, and tends to move the barrier height location toward the source. The electron and hole concentration in the channel will increase with an increase in the gate bias voltage. In response to low gate bias voltages, injected electrons flowing from the source region tend to combined around the channel center, while they distribute almost uniformly over the cross-sectional direction of the channel between paired gates at the high gate bias voltages such as 0.8 V. At V.sub.G =0.8 V, the hole concentration is nearly equal to the electron concentration in the channel near the source region. FIG. 3 indicates that there appears a virtual drift base region in the channel where the space charge is almost completely compensated for due to the injected electrons and the injected holes.
FIGS. 4 and 5 indicate that electrons are injected into the channel from the source region and their concentration is over 1.times.10.sup.17 cm.sup.-3 in spite of the low impurity concentration in the channel (such as 1.times.10.sup.14 cm.sup.-3). This fact insures the basic characteristics of BSIT such as high current density, high transconductance and so on. A BSIT usually exhibits a saturating current-voltage characteristic which seems to originate from the appearance of the virtual base region in the channel.
FIG. 4 indicates that there exists hole injection from the channel to the n.sup.+ type source region where the injected hole concentration is about 3.times.10.sup.15 cm.sup.-3 in the source region at V.sub.G =0.8 V. On the other hand, FIG. 5 indicates the existence of electron injection from the channel to the p.sup.+ type gate region. Their amount is up to 1.times.10.sup.16 cm.sup.-3 at V.sub.G =0.8 V. The minority carrier injection into the source and the gate region from the channel constitutes the gate current, and increases its magnitude, thus leading to a decrease in the current gain of BSIT, at high gate bias operation. The number of fan-outs is determined by the driving capability of inverter transistor and the input impedance or the current gain of the inverter transistor of the subsequent stage. The decrease in the input impedance or the current gain will serve to decrease the number of fan-outs. Propagation delay time is determined mainly by the ratio of the input capacitance to the driving capability. The propagation delay decreased with a decrease in the input capacitance, and with an increase in the driving capability. Also, where an SIT is employed as a switching device or as a memory device, the minority carrier injection will constitute a limitation on the switching characteristic, switching time, memory state or the like.